Job Description

Appealing points: 

• Engage in cutting-edge physical design from floor planning to timing closure, maximizing chip performance!
• Enhance your expertise using industry-leading EDA tools (Cadence, Synopsys, Mentor Graphics) for PPA optimization and verification.
• Collaborate closely with RTL and DFT engineers in a dynamic, teamwork-driven environment to deliver high-quality designs.

Annual Salary: 7 Million and above

Job Qualification:

• Design Implementation: Perform physical design tasks including floor planning, placement, clock tree synthesis, routing, and timing closure.
• Verification: Conduct physical verification tasks such as DRC (Design Rule Check), LVS (Layout vs. Schematic), and ERC (Electrical Rule Check).
• Optimization: Optimize designs for power, performance, and area (PPA).
• Collaboration: Work closely with RTL design engineers, DFT (Design for Test) engineers, and other team members to ensure design specifications are met.
• Tool Usage: Utilize EDA tools (e.g., Cadence, Synopsys, Mentor Graphics) for physical design and verification

Language Skills :Japanese language is plus, not manadatory

Company

This company is a leading foreign-affiliated solutions and services provider in the information, communications, and technology (ICT) industry. With more than 130,000 employees in 90 countries, they provide innovative IT solutions to nearly 1000 global customers, including Fortune 500 companies.

Measures against passive smoking

No smoking indoors allowed

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